I know we all heard about the "Cell 3" with 32 SPEs and 2 PPEs. Apparently, that has changed. The new possible chip
design is 32 SPEs and 4 PPEs (page 10).
Here are some highlights:
100% backward compatible
Performance on PPE significantly better
Performance per SPE equal or better
– Significantly better on applications that benefit from new instructions
Better inter-SPE latency
More on-chip memory
Better main memory latency and bandwidth
They are aiming for 1 TeraFLOPS performance from that chip!
Just as a reference, the Cell in the PS3 is capable of 204 GigaFLOPS. This is projected for 2010/2011. 2011 is probably when we will see the PS4. I doubt this is a coincidence.
